Saturday, February 05, 2005

Tower to lose chairman and CEO to "other interests": "Carmel Vernia, chairman of the board and chief executive officer of foundry Tower Semiconductor Ltd. (Migdal Haemek, Israel), has told the board of directors that he wishes to step down from his positions to pursue other interests, Tower said Friday (Feb. 4).
Vernia has agreed to stay in his current positions while the board appoints his replacements to ensure a smooth transition. Vernia would continue to serve on the board of directors of Tower after stepping down as chairman and chief executive officer, Tower said in a statement.
Tower, a pure-play independent wafer foundry founded in 1994, has struggled with profitability while it has acquired and developed close to leading edge process technology and brought up its second wafer fabrication facility. Fab 2 features 0.18-micron and below process technologies.When complete, Fab 2 is expected to offer full production capacity of 33,000 200mm wafers per month."

Thursday, February 03, 2005

Japan to launch mask e-beam, wafer inspection consortium: "Looking to address the soaring costs of photomasks at the 45-nm node and beyond, a Japanese R&D organization is proposing and putting the pieces together to form a reticle-writing electron-beam and wafer inspection consortium in Japan.
The group, tentatively called the Mask Writer Consortium, is being spearheaded by the Association of Super-Advanced Electronics Technologies (ASET), an R&D organization based in Tokyo.
The consortium hopes to develop high-speed e-beam and wafer inspection tool technologies for advanced photomasks at the 45-nm node. On the e-beam side, the consortium includes four Japanese companies that compete in this arena - Advantest Corp., Japan Electron Optical Laboratory Ltd. (JEOL), Hitachi High Technologies Ltd., and NuFlare Technology Inc.
The wafer inspection part of the group is expected to include two major chip makers: NEC Corp. and Toshiba Corp.
ASET has put a proposal together and hopes to receive funding from a Japanese government agency called the New Energy and Industrial Technology Development Organization (NEDO). The agency is responsible for R&D project planning and formation, project management and post-project technology evaluation.
The consortium is proposing some US$500,000 in funding for the first year and US$20 million in the second year. Officials from ASET believe there is a 90 percent chance that it will receive the funding from NEDO for the project, which is slated to take four years.
'ASET will start the project in June of 2005,' said Shinji Okazaki, director of EUV process technology research at ASET, in an interview. 'The goal of the consortium is to reduce exposure and wafer inspection costs.' "

Tuesday, February 01, 2005

Air Gaps Are a Low-k Alternative: "Let's face it. The air gap is a pretty crazy idea. Rather than filling the space between interconnecting wires with anything that would increase line-to-line capacitance and RC delay, just go straight for the best performing low-k dielectric of all: Air. More unusual things have happened.
Like effectively taking sandpaper to your device - later perfected into the state-of-the-art technology of CMP. And purposely engineering strain into the channel of transistors to increase performance. Balancing the stresses of tensile and compressive within nanometers in a device to separately optimize PMOS and NMOS transistors is both brilliant and, as it turns out, manufacturable. So when scaling gets really tough, engineers find alternatives.
The air gap may be the alternative to porous low-k dielectrics that the industry needs at this time. Porous dielectrics have too many problems - at least as many as their dense counterparts - and the overall benefit they deliver, represented as the effective k value, may be small given the integration, yield and reliability challenges they pose and the costs required to surmount them."

Monday, January 03, 2005

Taiwan will have the world's most chip foundries: "Taiwan is expected to have the most semiconductor foundries in the world by 2006, Minister of Economic Affairs Ho Mei-yueh said yesterday.
Ho said that there are currently four 12-inch wafer plants in Taiwan, in addition to six under construction and two others that are to be built soon.
By 2006, Taiwan will have 10 12-inch semiconductor foundries, more than the US' seven, Japan's five and South Korea's two, Ho said.
Coupled with the existing 20 eight-inch, eight six-inch and three five-inch wafer plants, the competitiveness of Taiwan's semiconductor industry is expected to remain strong.
Ho made the remarks after some people expressed their concern that the nation may lose its competitiveness in the semiconductor sector, as the government is moving to further ease restrictions on chip investment across the Taiwan Strait.
After Taiwan Semiconductor Manufacturing Co started producing 5,000 eight-inch wafers per month in China by the end of last year, several Taiwanese chip firms also decided to set up plants on the mainland in a move to safeguard their market position."

Sunday, January 02, 2005

How KLA-Tencor yields innovation: "Like any other good CEO, Ken Schroeder of KLA-Tencor spends a lot of time thinking about his employees. But unlike most other CEOs, he spends a lot of time thinking about what they know and what they still need to learn.
'We've been recognized as No. 1 in Silicon Valley for all kinds of training. We put a lot of time and attention into it. We emphasize unique training that makes us different,' says Schroeder, 59, who has led the semiconductor process control and yield management company since 1999.
The emphasis on learning apparently works. For one thing, it contributes to employee turnover of less than 5 percent on a global basis. And the learned staff's outpouring of innovative products has kept KLA-Tencor on the leading edge for more than two decades. The 28-year-old company has more than a 50 percent share of the process control market, with 70 percent in some segments. Its closest rival, Applied Materials, has about 10 percent. KLA-Tencor sells more than two dozen products for wafer inspection, mask inspection and metrology. It is No. 1 in most segments and No. 2 in the others. More important, analysts say, it is the only vendor that offers a portfolio of integrated tools that analyze defects data and helps users make corrective decisions. The arcane technology improves fab yields and allows chip makers to ramp up quickly in each new process as they follow Moore's Law. "

Friday, December 31, 2004

Predictions for IC, equipment biz in 2005 and beyond: "Happy Holidays! Silicon Strategies has compiled a list of 15 predictions for the IC and chip-equipment industries in 2005 and beyond. The predictions come from crystal balls at Silicon Strategies and various analysts. "

Saturday, December 18, 2004

August Technology Adds to Patent Portfolio; Intellectual Property is the Foundation of Inspection Leadership: "August Technology Corporation (NASDAQ:AUGT), a leading supplier of inspection, metrology and defect analysis solutions for the microelectronic industries, today announced it has received a new U. S. patent, number 6,826,298, for its continuous, on-the-fly inspection technology.
The patent supports August Technology's advanced macro, high-speed, model-based inspection technology which uses strobe illumination to freeze motion while continuously moving a wafer. This type of inspection is used to detect defects on whole, sawn and partial wafers throughout the device manufacturing process. Typical defects include particles, residue, scratches, corrosion, and edge and solder bump defects. "

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